For high speed circuitry it is desirable to have devices, such as transistors, with both p and n-type gates to allow for smaller device sizes while enabling the high speeds. For example, in DRAM processes, both p+ and n+ gate electrodes are used to allow both high speed processing and smaller sizes.
Many system-on-chip (SOC) designs include both high speed digital circuitry and analog circuitry. Image sensors are examples of apparatuses that can have an SOC design. Image sensors typically include an array of pixel cells and peripheral circuitry for signal processing. Ideally, image sensors would be capable of analog signal processing in addition to high speed digital processing. High speed image sensor circuitry requires small gate length devices compatible with high drive currents and low threshold voltages, whereas analog signal transmitters, particularly in a pixel array, have much different operating characteristics where high quantum efficiency is more important than speed. This is true for both PMOS and NMOS devices.
Conventional NMOS devices use n+ polysilicon gate electrodes over a substrate having a p-well. Such devices are surface channel devices. If the same n+ polysilicon gate electrode is used in connection with an n-well in a PMOS device, the threshold voltage becomes too high. However, using n+ gates throughout an image sensor or any other integrated circuit is a low cost process. To accommodate n+ gate electrodes in PMOS devices, a p-type implant is used at the substrate n-well surface to create a buried junction in the channel region of the transistor. Using a “buried channel” PMOS device has significant drawbacks. For example, such a device does not scale down to smaller sizes well, due to poor electrostatic gate control and, therefore, poor short-channel effects.
It would be desirable to use both p+ and n+ gate electrodes having different operating characteristics in integrated circuits. However, conventional methods for fabricating integrated circuits having both p+ and n+ gate electrodes is not well suited for providing both p+ and n+ gate electrodes each having different operating characteristics in a single integrated circuit. One of the biggest challenges in the process flow used to fabricate both p+ and n+ gate electrodes is to keep the dopant types, particularly p-type dopants, such as boron, from diffusing through the gate oxide into the channel regions of the devices during the thermal processing steps. N-type dopants, such as phosphorus and arsenic, have relatively low diffusivity through oxides and therefore, are not a primary concern. To address this problem, it has become standard to uniformly use nitrided gate oxides when both p+ and n+ gate electrodes are used.
Nitrided gate oxides, however, are known to have significant disadvantages, particularly in noise sensitive integrated circuits such as image sensors. For example, when a nitrided gate oxide is used, the interface between the gate oxide and substrate surface is poor. Further, nitrided oxides cause fluctuation in transistor characteristics, such as carrier mobility, transconductance, trapping, de-trapping, among others, which are undesirable in analog circuitry. Additionally, nitrided gate oxides used in pixels significantly increases noise, particularly “1/f” or random telegraph signal “RTS” noise in image sensors, which is undesirable.
What is needed is a method and apparatus which mitigates the drawbacks noted with conventional nitrided gates, but which provides an integrated circuit, e.g., and image sensor integrated circuit, with n and p-type gates and with different types of n and p-type gates in an integrated circuits. Additionally, it is desirable to have a variety of devices having different threshold voltages for use in circuit designs.